IPhO 2018, Експеримент — Задача 1. Paper transistor

Paper transistor (10 points) · 23 юли 2018 г. · 10 т.

Official key edition

Solutions to Experimental Problem 1 — Paper transistor. Authors: Elvira Fortunato, Luís Pereira, Rui Igreja, Paul Grey, Inês Cunha, Diana Gaspar, Rodrigo Martins. July 23, 2018, v1.4. The obtained historical key carries a “Confidential” watermark.

Условие

Electronic technology in modern society is based on a simple, yet powerful device: the transistor, which can be used both as a switch and as an amplifier. The switch mode is used for storage and processing of digital information.

Here we will analyse two types of Field Effect Transistors (FET): JFET (Junction Field Effect Transistor) and the TFT (Thin Film Transistor).

We shall briefly explain here how a FET works. A FET is a non-linear 3 terminal device (the terminals being named Gate: G; Source: S; and Drain: D) that can control the current flow between Source and Drain by acting upon the voltage applied between the Gate and the Source. In a simple, although imperfect analogy, a FET works similarly to a water tap, the knob acting as the Gate controlling the water flow.

The Junction-FET (JFET) relies upon the properties of the junction between two types of a semiconducting material, such as p and n doped silicon, hence its name. A JFET has a narrow channel through which the current flows between Source and Drain, and in a n-channel FET this channel is made of n-type material. The width of such channel can be controlled in a precise way by applying a negative voltage between the Gate and the Source, $V_{GS}=V_G-V_S$. For a fixed $V_{GS}$, the current flowing between Source and Drain depends non-linearly on the applied voltage between Drain and Source, $V_{DS}=V_D-V_S$. For small $V_{DS}$ voltages, however, the current does depend linearly on the applied voltage, thus the JFET displays ohmic behaviour. The output resistance, $R_{DS}=V_{DS}/I_{DS}$, however, does depend strongly on the applied $V_{GS}$ voltage, closely following the law:

where $R_{DS}^0$ is the output resistance at $V_{GS}=0$ and $V_P<0$ is a JFET parameter called the pinch-off voltage. Clearly, at the pinch-off voltage, the FET blocks current flow.

For any fixed $V_{GS}>V_P$, the current between Source and Drain will start to depart from the linear behaviour as we increase $V_{DS}$, and will at some point saturate at an almost constant value. Let $I_{DSS}$ be the saturation current when $V_{GS}=0$. In the saturation regime (large applied $V_{DS}$), the saturation current will depend on $V_{GS}$ in the following way:

We should stress two very important characteristics of a JFET. Although its voltage controlled output resistance can be quite low, the input resistance ($R_{GS}=V_{GS}/I_{GS}$) is extremely high, typically larger than $10^9\ \Omega$, so this device uses very little input current. Also, the capacitance of a small JFET is quite low making it a very fast device than can 'open and close' beyond MHz rates.

We now proceed to describe how a different type of FET, the TFT, works.

As any other FET, the TFT permits the control of a current between two contacts, the Drain and Source electrodes, by means of an applied potential at the third electrode, the Gate.

The Gate electrode is physically separated from the semiconductor layer by a dielectric that allows for the establishment of a vertical electrical field that will control the free charge carriers existing in the semiconductor (field effect). The dielectric layer can be replaced by an electrolytic membrane such as paper where mobile ions exist (see Figure 2) and in this case the voltage applied at the Gate will push ions with opposite charge to the semiconductor interface, creating a sheet of ionic charges that will modulate the free carriers' density existing within the semiconductor (Electrolyte Gated Transistors - EGTs). Researchers at Universidade Nova, Lisbon, were pioneers in developing in 2008 the "paper transistor", and are world leaders in this field.

Similarly to JFETs, TFT transistors can operate in two fundamental operation modes, a linear mode and a saturation mode. In contrast to JFET, TFT intrinsic capacitance is a relevant parameter for the device performance.

In this experimental problem you will examine how an n-channel JFET and a paper TFT work.

You will determine the Characteristic Curves (CCs) of these devices by measuring the current between S and D ($I_{DS}$) through the application of distinct voltages at G ($V_{GS}$) and D ($V_{DS}$).

The two most important CCs are the output and the transfer curves:

• Output Curve: For this curve the current between Source and Drain ($I_{DS}$) will be measured and plotted as a function of the voltage between Source and Drain ($V_{DS}$), with $V_{DS}$ swept from $0\ \mathrm V$ up to $+3\ \mathrm V$, in steps, while keeping $V_{GS}$ constant.
• Transfer Curve: For this curve $I_{DS}$ will be measured and plotted against $V_{GS}$. $V_{DS}$ will be kept constant at a suitable value for the transistor to work in the saturation mode and $V_{GS}$ will be swept in steps from $-3$ to $0\ \mathrm V$.

Equipment

The following set of equipment (Figure 3) is provided for this experimental problem:

1. multimeter
2. JFET transistor (provided inside a labelled plastic bag)
3. cables (10) with alligator clips
4. flat alligator clips (4, provided inside a plastic bag)
5. battery pack ($4\times1.5\ \mathrm V$)
6. battery holder
7. mini-breadboard with support
8. jumper wires (3) to connect to the mini-breadboard
9. HB pencil
10. silver ink conductive pen (Circuit Scribe)
11. chronometer
12. sheet of paper with printed circuits and an embedded TFT that uses paper as dielectric layer (Figure 4)
13. bag with writing material (1 pen, 1 pencil, 1 eraser/sharpener, 1 ruler)

Important precaution:

Do not fold the sheet of paper with the printed circuits and embedded transistor as this will easily damage it. Try to leave it as flat as possible during measurements in order to reach best results.

For the measurements it is important to take into account the following important information:

• The multimeter should always be operated in DC mode.
• The multimeter does not autorange and you should carefully choose the most appropriate ranges for your measurements. In case a overflow occurs the display will show either "1" or "-1" (left justified on the display), for positive and negative values, respectively, and you should change to a lower range.
• The low-current ranges are protected by a $315\ \mathrm{mA}$ fuse. Avoid by all means to create a short circuit between the battery and the multimeter because a high current will blow up the fuse!
• The internal resistance of the multimeter when operating in voltmeter mode is $10\ \mathrm{M\Omega}$.
• When operating as ammeter, the internal resistance of the multimeter depends on the range as shown in the following table:

Table 1. Internal resistance of the provided multimeter when operated as ammeter.

Thus, when the multimeter is being used in DC ammeter mode, there will be a voltage drop up to $200\ \mathrm{mV}$ between its terminals at full scale when operated in any of the 3 available DC ranges.

Source note: The original overflow instruction says “change to a lower range”; that printed instruction is retained.

Part A. Circuit dimensioning (2.5 points)

To achieve the necessary $V_{DS}$ and $V_{GS}$ voltages you will use two carbon resistors printed on paper ($R_1$ and $R_2$, see Fig. 4) and voltage divider circuitry to dimension the circuit for the right potential drops. $R_1$ and $R_2$ will be the total resistance ($R_{tot}$) of a voltage divider circuit. When applying a constant voltage (in this case about $3\ \mathrm V$ from the battery) across $R_1$, for instance, we will see a voltage drop along it from $3\ \mathrm V$ ($V_{in}$, the positive contact of the battery) to ground ($0\ \mathrm V$; from now on, we designate as ground the common contact of the two battery packs). $R_{tot}$ can be divided into essentially two resistances ($R_x$ and $R_y$) to achieve the desirable $V_{out}$ (Figure 5).

A.1 Write down the expression for the output voltage, $V_{out}$, as a function of $V_{in}$ and resistances $R_x$ and $R_y$. [0,2 т.]

A.2 Measure the resistance of the three test resistors on the bottom part of the sheet ($R_{T1}$, $R_{T2}$ and $R_{T3}$) with the multimeter. Carry out enough measurements with different positions on the silver contacts. Enter the values in the Answer Sheet. Calculate the average value and estimate the uncertainty for the resistance of each test resistor. [0,5 т.]

A.3 Show that the resistance of a square thin film with a certain resistivity, $\rho$, should be independent of the length of its side. This size-independent resistance is called sheet resistance and is denoted $R_{\square}$. [0,3 т.]

A.4 Calculate the average value of the sheet resistance of the carbon film from the data in A.2 and obtain the resistivity, $\rho$, of the carbon film with an estimation of its uncertainty (consider a thickness $t$ of the carbon film of $20\pm1\ \mathrm{\mu m}$). [0,4 т.]

A.5 Show that the theoretical value of the $R_1$ and $R_2$ resistances is $R_1=R_2=\kappa R_{\square}$, $\kappa\sim14.2897$. Measure $R_1$ and $R_2$ and write down the values in the Answer Sheet. Determine the experimental value of $\kappa$ and compare it with the theoretical value. [0,5 т.]

Using the provided silver ink pen, draw 7 equally spaced conductive lines along each of the provided resistors (as exemplified in Figure 6). These individual lines will serve as the contact points for the voltage dividers.

A.6 Measure the resistances $R_x$ and $R_y$ for all contact points. $R_x$ is defined as the resistance between the contact point and points V (resistor 1) or W (resistor 2), and $R_y$ is defined as the resistance between the contact point and point Z. Fill the provided tables in the Answer Sheet. [0,3 т.]

Insert the 4 AA batteries in the battery holder. Please observe carefully the correct battery polarity and make sure you do not produce a short circuit. Then, physically connect the battery pack as depicted in Figure 7. Make sure you do not damage the silver tracks with the alligator clips.

A.7 Measure $V_{out}$ at each contact point, $V_{out}$ being the voltage measured with respect to point Z and enter the values in the provided tables in the Answer Sheet. [0,3 т.]

This concludes the circuit dimensioning part and you can now proceed to measure the CCs of the JFET transistor.

Part B. Characteristic Curves of the commercial JFET transistor (4.5 points)

In order to characterise the JFET transistor you will use the setup depicted in Figure 8. Start by identifying the three contacts (S, D and G) on the provided JFET transistor - pay attention to the correct identification of the contacts, as the device is not symmetric! You may use the provided minibreadboard with support to mount the JFET transistor. The provided jumper wires are to be used with the mini-breadboard.

Using the provided cables, connect the Gate and the Source of the transistor to ground (point Z of the circuit, at $0\ \mathrm V$). Throughout this part of the problem, the Source of the JFET should always be kept connected to ground.

B.1 Connect the gate of the transistor to ground ($V_{GS}=0$). Then connect one of the cables of the multimeter, that should be used in DC current mode, to the drain of the transistor and with the other cable touch the point with the highest voltage available in the voltage dividers. Write down in the answer sheet the value of the current $I_{DS}$. [0,2 т.]

B.2 Measure the current $I_{DS}$ for different positive voltages applied to the Drain, while keeping $V_{GS}=0$. Then change the circuit to apply a negative voltage between the Gate and the Source of the transistor ($V_{GS}<0$) and repeat the measurements of $I_{DS}$ as a function of the positive applied voltage between Drain and Source. Fill with your values the tables provided in the Answer Sheet. [0,8 т.]

When the voltage divider circuit is connected to a low resistance load (Figure 9), the voltage values provided by the voltage divider, $V_{out}^L$, are different from the nominal values $V_{out}$ measured when the load is a high resistance, such as the case of a high impedance voltmeter.

B.3 Consider that the voltage divider is connected to a load $R_L$. Obtain an expression for the correction factor $f=V_{out}^L/V_{out}$ as a function of $R_L$, $R_x$ and $R_y$. [0,2 т.]

The JFET transistor has a low output resistance when $V_{GS}=0$, namely $R_{DS}^0\sim50\ \Omega$. However, this resistance increases significantly when the Gate is polarised negatively with respect to the Source. For $V_{GS}<0$ the output resistance follows closely the law given by equation (1).

B.4 Using the appropriate correction factors, calculate $V_{DS}$, the voltage drop between Drain and Source, for all the points measured in B.2. Consider the following nominal data for the JFET used in this problem: $R_{DS}^0=50\ \Omega$, $V_P=-1.4\ \mathrm V$. [1,2 т.]

B.5 Plot the output curves $I_{DS}(V_{DS})$ for your JFET transistor. [0,5 т.]

B.6 Consider the transistor in operation at small $V_{DS}$. Obtain the experimental values of $R_{DS}$ of your JFET for different $V_{GS}$ and plot the data. [0,5 т.]

B.7 Plot the transfer curve $I_{DS}(V_{GS})$ of your JFET transistor for $V_{DS}\sim+3\ \mathrm V$. [0,3 т.]

When the JFET transistor is in saturation mode, the current $I_{DS}$ follows closely the law expressed by equation (2).

B.8 From the measured data, obtain $I_{DSS}$ and the pinch-off voltage, $V_P$, for your device. Compare the value obtained of $V_P$ with the nominal value. [0,4 т.]

An important parameter of a JFET transistor, in particular when it is used in amplifiers, is the so called transistor transconductance, $g$, defined as

For a function of two variables $f(x,y)$, the notation $\frac{\partial f}{\partial x}$ means the derivative of $f$ with respect to $x$ when $y$ is kept constant.

B.9 Obtain, from the measured transfer curve, the transconductance of your device for $V_{GS}=-0.50\ \mathrm V$. Compare it with the calculated value obtained from the model equation (2). [0,4 т.]

Part C. The Paper Thin Film Transistor (2.0 points)

From now on, you discard the JFET, and all following tasks and questions relate to the paper thin film transistor (TFT) located in the upper corner of the printed circuit. The TFT Gate, Source and Drain are marked in Figure 10. Connect the TFT Gate and the Source to ground. Also in this part of the problem the Source of the paper TFT should always be connected to the common contact of the battery packs, i.e. $0\ \mathrm V$, as shown in Figure 10. Polarise the transistor with $V_{DS}>0$, via one of the voltage circuit dividers (Figure 10). Check that a current is flowing through the ammeter.

C.1 Apply $V_{DS}=+3.0\ \mathrm V$. Close the transistor by applying $V_{GS}=-3.0\ \mathrm V$. Wait for $1\ \mathrm{min}$ so that the the transistor closes. Write down in the answer sheet the residual value of the current, $I_{closed}$. Then open the transistor by putting $V_{GS}=0$, while keeping $V_{DS}=+3.0\ \mathrm V$. Measure the current as function of time, starting at the instant when you open the transistor, for at least $5\ \mathrm{min}$ and collect the data $I_{DS}(t)$ in the answer sheet. [0,8 т.]

C.2 Plot $I_{DS}(t)$. There is a superposition of two exponential processes in the time dependence, one with a much larger time constant ($\tau_2$) than the other ($\tau_1$). Determine the shorter time constant, $\tau_1$. [1,2 т.]

Part D. Inverter circuit (1.0 points)

In microelectronic circuitry one of the most important circuits is the inverter, that is able to invert a digital input. For instance if $V_{in}=\text{high}$ then $V_{out}=\text{low}$ and vice-versa. A transistor is once again at the basis of the circuit and one of the simplest designs is the so called common source amplifier, depicted in Figure 11, using a transistor and a load resistance ($R_L$). In this case $V_{in}=V_{GS}$ and $V_{out}$ is the voltage measured at the Drain electrode of the transistor. Thus, in this part we will monitor what happens to $V_{out}$ while sweeping $V_{GS}$ from $-3\ \mathrm V$ to $0\ \mathrm V$.

In the setup of Figure 11 the transistor is the paper TFT and $R_L$ is a load resistance you are going to add now, manually, by connecting the Drain contact of the transistor with the Vin contact using a pencil track, as indicated in Figure 12. While you write, you are actually depositing thin layers of conductive graphite on the paper so the more layers you draw on top of each other, the lower the resistance will get. While drawing $R_L$ make sure to continuously monitor its resistance. To pull Vout as close to $0\ \mathrm V$ as possible the load resistance should be large enough. So, while drawing the resistance, aim for a value close to the target value $R_L=200\ \mathrm{k\Omega}$.

You can either use the pencil to decrease $R_L$ or the eraser to increase it. You should aim to obtain a value differing not more than 10% from the aimed value.

Use the included HB pencil and draw by hand a carbon resistor with value of $R_L\simeq200\ \mathrm{k\Omega}$ to be used as a load resistor of the paper TFT to build the inverter circuit (see Figure 12).

D.1 Write down in the Answer Sheet the measured $R_L$ value you have reached. Setup the inverter circuit (Figure 12) using the carbon track resistor and the paper TFT. Before the measurement, remember that you should turn the transistor fully off by applying $V_{GS}=-3\ \mathrm V$ and wait for $\sim1\ \mathrm{min}$. Then measure $V_{out}$ as you sweep $V_{GS}$ from $-3\ \mathrm V$ to $0\ \mathrm V$ and take readings of $V_{out}$ with a stabilization time for each point up to a maximum of $100\ \mathrm s$. Enter the measured values in the Answer Sheet. [0,5 т.]

D.2 Plot the measured $V_{out}(V_{in})$ voltage transfer curve and draw a smooth trend curve through the data points. [0,5 т.]

Native answer sheets

These are the blank forms from the obtained 15-page official answer-sheet companion, in native page order. Blank cells and fields are deliberately left blank. They are not additional tasks or measured data.

Answer sheet A1-1

Write down the numbers 0 to 9 in the following table:

Part A: Circuit Dimensioning (2.5 points)

A.1 (0.2 pt)

$V_{out}=\underline{\qquad}$

A.2 (0.5 pt)

Answer sheet A1-2

A.3 (0.3 pt)

Demonstration:

A.4 (0.4 pt)

$R_{\square}=\underline{\qquad}\pm\underline{\qquad}$

$\rho_{\text{Carbon film}}=\underline{\qquad}\pm\underline{\qquad}$

A.5 (0.5 pt)

Demonstration:

Measured values:

$R_1=\underline{\qquad}$

$R_2=\underline{\qquad}$

$\kappa=\underline{\qquad}$

Answer sheet A1-3

A.6 (0.3 pt)

Resistor $R_1$:

Resistor $R_2$:

A.7 (0.3 pt)

Answer sheet A1-4

Part B: Characteristic Curves of the JFET transistor (4.5 points)

B.1 (0.2 pt)

$I_{DS}=\underline{\qquad}$

B.2 (0.8 pt)

$I_{DS}$ current values:

B.3 (0.2 pt)

$f=\underline{\qquad}$

Answer sheet A1-5

B.4 (1.2 pt)

Use the empty columns to enter corrections factors you deem necessary.

Gate A:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Gate B:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Answer sheet A1-6

B.4 cont.

Gate C:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Gate D:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Answer sheet A1-7

B.4 cont.

Gate E:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Gate F:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Answer sheet A1-8

B.4 cont.

Gate G:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Gate V:

$V_{GS}=\underline{\qquad}$

$R_{DS}=\underline{\qquad}$

Answer sheet A1-9

B.5 (0.5 pt)

Output curves:

Answer sheet A1-10

B.6 (0.5 pt)

Graph: $R_{DS}(V_{GS})$

Answer sheet A1-11

B.7 (0.3 pt)

Transfer curve:

B.8 (0.4 pt)

$I_{DSS}=\underline{\qquad}$

$V_P=\underline{\qquad}$

B.9 (0.4 pt)

Measured transconductance: $g=\underline{\qquad}$

Calculated transconductance from JFET model: $g=\underline{\qquad}$

Answer sheet A1-12

Part C: The Paper Thin Film Transistor (2.0 points)

C.1 (0.8 pt)

$I_{closed}=\underline{\qquad}$

Answer sheet A1-13

C.2 (1.2 pt)

Graph: $I_{DS}(t)$

Auxiliary graph to determine $\tau_1$:

$\tau_1=\underline{\qquad}$

Answer sheet A1-14

Part D: Inverter circuit (1.0 points)

D.1 (0.5 pt)

$R_L=\underline{\qquad}$

Answer sheet A1-15

D.2 (0.5 pt)

Graph: $V_{out}(V_{in})$

Решение

Теми и трудност

Оценена трудност: 4/5.

Електричество · Съвременна физика · Постояннотокови вериги · Полупроводници · Преходни процеси в RC вериги

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Оригинал в Архива: exp1.pdf · официални решения: exp1_sol.pdf · допълнителни данни: exp1_anssheet.pdf